The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Apr. 10, 2018
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Kiyohiro Hine, Osaka, JP;

Akio Furusawa, Osaka, JP;

Hidetoshi Kitaura, Osaka, JP;

Kazuki Sakai, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 23/498 (2006.01); H01L 23/15 (2006.01); H01L 23/14 (2006.01); H01L 33/62 (2010.01); H01L 33/64 (2010.01); H01L 21/48 (2006.01); B23K 35/30 (2006.01); B32B 9/00 (2006.01); B32B 15/20 (2006.01); C22C 5/02 (2006.01); H01L 23/00 (2006.01); B23K 101/36 (2006.01); B23K 103/12 (2006.01); B23K 103/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3735 (2013.01); B23K 35/3013 (2013.01); B32B 9/005 (2013.01); B32B 15/20 (2013.01); C22C 5/02 (2013.01); H01L 21/4857 (2013.01); H01L 21/4882 (2013.01); H01L 23/142 (2013.01); H01L 23/15 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49866 (2013.01); H01L 24/26 (2013.01); H01L 33/62 (2013.01); H01L 33/641 (2013.01); H01L 33/647 (2013.01); B23K 2101/36 (2018.08); B23K 2103/12 (2018.08); B23K 2103/52 (2018.08); B32B 2457/00 (2013.01); H01L 2224/83101 (2013.01);
Abstract

A mount structure having a joining capable of withstanding development of cracks generated by thermal stress due to repeated temperature changes in a mount structure having the joining of a large area is formed by joining a ceramic substrate electrode of a ceramic substrate and a metal substrate electrode of a metal substrate by a laminate, in which the laminate is formed by stacking a first interface layer, a first solder joining portion, a second interface layer, a first buffer material electrode, a buffer material, a second buffer material electrode, a third interface layer, a second solder joining portion and a fourth interface layer in this order from the ceramic substrate electrode toward the metal substrate electrode, a thickness of the laminate is 30 μm or more and 100 μm or less, a difference between a thickness of the first solder joining portion and a thickness of the second solder joining portion is within 25%, and differences in elastic moduli and in linear expansion coefficients between the first solder joining portion and the buffer material are respectively within 62%.


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