The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Jun. 30, 2018
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Xiaohai Wu, Fremont, CA (US);

Roland Ruehl, San Carlos, CA (US);

Tao Hu, Fremont, CA (US);

Walter Ghijsen, San Jose, CA (US);

Yujia Li, Santa Clara, CA (US);

An-Chang Deng, Saratoga, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/505 (2013.01); G06F 2217/02 (2013.01);
Abstract

Various techniques implement an electronic design with hybrid analysis techniques. An activity map is identified or generated for an electronic design. The electronic design is reduced into a reduced electronic design at least by applying a plurality of reduction processes to different portions of the electronic design based in part or in whole upon the activity map. Transient behaviors of the electronic design may be determined or predicted at least by performing one or more transient analyses on a representation of the electronic design with a simulation start point based in part or in whole upon the activity map. The electronic design may then be implemented for manufacturing at least by modifying or correcting the electronic design based at least in part upon the transient behaviors.


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