The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Jun. 29, 2018
Applicant:

Sensor Electronic Technology, Inc., Columbia, SC (US);

Inventors:

Rakesh Jain, Columbia, SC (US);

Maxim S. Shatalov, Columbia, SC (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 33/00 (2010.01); H01L 31/18 (2006.01); C30B 29/40 (2006.01); C23C 16/02 (2006.01); C23C 16/34 (2006.01); C30B 25/18 (2006.01); C23C 16/56 (2006.01); C23C 16/30 (2006.01); C30B 29/68 (2006.01); H01L 33/32 (2010.01); H01L 33/12 (2010.01);
U.S. Cl.
CPC ...
H01L 33/0075 (2013.01); C23C 16/0272 (2013.01); C23C 16/303 (2013.01); C23C 16/34 (2013.01); C23C 16/56 (2013.01); C30B 25/183 (2013.01); C30B 25/186 (2013.01); C30B 29/403 (2013.01); C30B 29/406 (2013.01); C30B 29/68 (2013.01); H01L 21/0254 (2013.01); H01L 21/02458 (2013.01); H01L 21/02505 (2013.01); H01L 31/1848 (2013.01); H01L 31/1852 (2013.01); H01L 31/1856 (2013.01); H01L 31/1864 (2013.01); H01L 33/007 (2013.01); H01L 33/12 (2013.01); H01L 33/32 (2013.01);
Abstract

Semiconductor structures formed with annealing for use in the fabrication of optoelectronic devices. The semiconductor structures can include a substrate, a nucleation layer and a buffer layer. The nucleation layer and the buffer layer can be epitaxially grown and then annealed. The temperature of the annealing of the nucleation layer and the buffer layer is greater than the temperature of the epitaxial growth of the layers. The annealing reduces the dislocation density in any subsequent layers that are added to the semiconductor structures. A desorption minimizing layer epitaxially grown on the buffer layer can be used to minimize desorption during the annealing of the layer which also aids in curtailing dislocation density and cracks in the semiconductor structures.


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