The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2020
Filed:
Oct. 23, 2018
Semiconductor device having semiconductor regions with an interval therebetween in a gate pad region
Applicant:
Fuji Electric Co., Ltd., Kawasaki-shi, JP;
Inventors:
Yusuke Kobayashi, Tsukuba, JP;
Manabu Takei, Tsukuba, JP;
Shinsuke Harada, Tsukuba, JP;
Naoyuki Ohse, Matsumoto, JP;
Assignee:
FUJI ELECTRIC CO., LTD., Kawasaki, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/47 (2006.01); H01L 29/08 (2006.01); H01L 29/872 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 29/0615 (2013.01); H01L 29/0623 (2013.01); H01L 29/086 (2013.01); H01L 29/0878 (2013.01); H01L 29/1608 (2013.01); H01L 29/47 (2013.01); H01L 29/66068 (2013.01); H01L 29/7806 (2013.01); H01L 29/872 (2013.01);
Abstract
A vertical MOSFET having a trench gate structure includes an n-type drift layer and a p-type base layer formed by epitaxial growth. In the n-type drift layer, an n-type region, first p-type regions, and a second p-type region are provided. In a region opposing, in a depth direction, a gate electrode pad connected to a gate electrode, the first p-type regions are provided with intervals therebetween along a width direction of the trench gate.