The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Jan. 25, 2019
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Yunmo Chung, Yongin-si, KR;

Daewoo Lee, Yongin-si, KR;

Ilhun Seo, Yongin-si, KR;

Hojin Yoon, Yongin-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/32 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1233 (2013.01); H01L 27/124 (2013.01); H01L 27/1248 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01); H01L 27/14603 (2013.01); H01L 27/3262 (2013.01); H01L 27/3272 (2013.01);
Abstract

A display apparatus including a first thin film transistor disposed on a substrate and including a first active layer, a second thin film transistor disposed on the first thin film transistor and including a second active layer overlapping the first thin film transistor, a first planarization layer disposed between the first thin film transistor and the second thin film transistor, the first planarization layer including a first insulating layer and a second insulating layer disposed on the first insulating layer, and a first buffer layer disposed between the first planarization layer and the second thin film transistor, in which an upper surface of the second insulating layer and an upper surface of the first insulating layer are substantially flush with each other.


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