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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10629475 B1

PDFFull Text
Date of Patent:
Apr. 21, 2020

Filed:

Dec. 22, 2017

Semiconductor device with two-part insulation structure within non-active region

Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Hsin-Chih Lin, Hsinchu, TW;

Shin-Cheng Lin, Tainan, TW;

Yung-Hao Lin, Jhunan Township, TW;

Assignee:

VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION, Hsinchu, TW;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

Peter Bradford

Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/06 (2006.01); H01L 29/778 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76237 (2013.01); H01L 21/2654 (2013.01); H01L 21/30621 (2013.01); H01L 29/0653 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01); H01L 21/0242 (2013.01); H01L 21/0254 (2013.01); H01L 21/0262 (2013.01); H01L 21/02378 (2013.01); H01L 21/02381 (2013.01); H01L 21/02458 (2013.01); H01L 21/02502 (2013.01);
Abstract

A method for forming a semiconductor device is provided. A substrate is provided. An epitaxial layer is formed on the substrate. An insulation region and an active region are defined on the upper surface of the epitaxial layer. An insulation structure is formed within the insulation region by an ion implantation process and an etching process, wherein the insulation structure includes a first insulation structure and a second insulation structure. A gate is formed on the epitaxial layer and is disposed within the active region. A source and a drain are formed on opposite sides of the gate and within the active region. A semiconductor device is also provided.

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