The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Sep. 28, 2018
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Nian Niles Yang, Mountain View, CA (US);

Abhijeet Manohar, Bangalore, IN;

Assignee:

SanDisk Technologies LLC, Plano, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G06F 12/02 (2006.01); G11C 16/34 (2006.01); G06F 11/10 (2006.01); G11C 29/02 (2006.01); G11C 29/00 (2006.01); G11C 29/52 (2006.01); G11C 16/24 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5628 (2013.01); G06F 11/1012 (2013.01); G06F 11/1076 (2013.01); G06F 12/0246 (2013.01); G11C 11/5642 (2013.01); G11C 16/349 (2013.01); G11C 16/3445 (2013.01); G11C 16/3454 (2013.01); G11C 16/3495 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 29/78 (2013.01); G11C 16/24 (2013.01); G11C 29/52 (2013.01); G11C 2029/0401 (2013.01);
Abstract

A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.


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