The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2020
Filed:
Jun. 29, 2018
Nvxl Technology, Inc., Fremont, CA (US);
Federico Sambilay, Jr., Fremont, CA (US);
Bharadwaj Pudipeddi, San Jose, CA (US);
Richard A. Cantong, Fremont, CA (US);
Joevanni Parairo, Fremont, CA (US);
BiTMICRO Networks, Inc., Fremont, CA (US);
Abstract
In an embodiment of the invention, an apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; a field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA; wherein the apparatus triggers a switch of an FPGA image in the FPGA to another FPGA image. In another embodiment of the invention, a method comprises: triggering, by an apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image; herein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA. In yet another embodiment of the invention, an article of manufacture comprises a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising: triggering, by the apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image, wherein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA.