The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Dec. 12, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Riyas Noorudeen Remla, Singapore, SG;

Warren E. Cory, Redwood City, CA (US);

Chee Chong Chan, Singapore, SG;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/04 (2006.01); H03L 7/00 (2006.01); H03M 13/33 (2006.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
H04L 7/04 (2013.01); H03L 7/00 (2013.01); H03M 13/00 (2013.01); H03M 13/336 (2013.01);
Abstract

Electrical circuits and associated methods relate to performing a phase alignment by providing N copies of clock alignment circuits, enabling and selecting different clock alignment circuits to achieve an initial phase alignment. In an illustrative example, a phase alignment circuit may include a first clock alignment circuit configured to find a first phase alignment point and a second clock alignment circuit configured to find a second phase alignment point. A control circuit may be configured to select a primary clock alignment circuit from the first clock alignment circuit and the second clock alignment circuit and generate a digital command signal to control a phase interpolator. In various embodiments, by setting the control circuit, the same phase alignment circuit may be used to perform phase alignments between clock domains with different frequencies.


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