The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2020
Filed:
May. 03, 2019
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Andrew M. Greene, Albany, NY (US);
Ekmini Anuja De Silva, Slingerlands, NY (US);
Siva Kanakasabapathy, Pleasanton, CA (US);
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/3213 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 27/108 (2006.01); H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 21/32 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7856 (2013.01); H01L 21/28247 (2013.01); H01L 21/32139 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823857 (2013.01); H01L 27/0886 (2013.01); H01L 27/092 (2013.01); H01L 27/0924 (2013.01); H01L 27/10826 (2013.01); H01L 27/10879 (2013.01); H01L 27/1211 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/0228 (2013.01); H01L 21/02181 (2013.01); H01L 21/02274 (2013.01); H01L 21/32 (2013.01); H01L 21/321 (2013.01); H01L 21/823481 (2013.01); H01L 27/1207 (2013.01);
Abstract
Semiconductor devices include a semiconductor fin. A gate stack is formed over the semiconductor fin. Source and drain regions are formed at respective sides of the gate stack. A dielectric line is formed parallel to the gate stack. An interlayer dielectric is formed between the gate stack and the dielectric line. A top surface of the interlayer dielectric between the gate stack and the dielectric line is not recessed.