The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Aug. 19, 2018
Applicant:

Richtek Technology Corporation, Zhubei, Hsinchu, TW;

Inventors:

Tsung-Yi Huang, Hsinchu, TW;

Chu-Feng Chen, Hsinchu, TW;

YU-Ting Yeh, Miaoli, TW;

Assignee:

RICHTEK TECHNOLOGY CORPORATION, Zhubei, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 21/266 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/266 (2013.01); H01L 29/0865 (2013.01); H01L 29/0869 (2013.01); H01L 29/0882 (2013.01); H01L 29/1079 (2013.01); H01L 29/1095 (2013.01); H01L 29/4916 (2013.01); H01L 29/66681 (2013.01); H01L 29/66689 (2013.01); H01L 29/0692 (2013.01); H01L 29/0696 (2013.01); H01L 29/42368 (2013.01);
Abstract

A high voltage MOS device includes: a well, a body region, a gate, a source, plural body contact regions and a drain. The plural body contact regions are formed in the body region, wherein each of the body contact region is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the gate in the lateral direction. The plural body contact regions are arranged substantially in parallel in the width direction and any two neighboring body contact regions are not in contact with each other in the width direction. The gate includes a poly-silicon layer which serves as the only electrical contact of the gate, and every part of the poly-silicon layer is the first conductivity type.


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