The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10622368 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 14, 2020

Filed:

Aug. 03, 2016
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Senaka Kanakamedala, Milpitas, CA (US);

Raghuveer S. Makala, Sunnyvale, CA (US);

Rahul Sharangpani, Fremont, CA (US);

Somesh Peri, San Jose, CA (US);

Yao-Sheng Lee, Tampa, FL (US);

James Kai, Santa Clara, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11556 (2017.01); H01L 27/11524 (2017.01); H01L 27/11548 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 27/11524 (2013.01); H01L 27/11548 (2013.01);
Abstract

Azimuthally-split metal-semiconductor alloy floating gate electrodes can be formed by providing an alternating stack of insulating layers and spacer material layers, forming a dielectric separator structure extending through the alternating stack, and forming memory openings that divides the dielectric separator structure into a plurality of dielectric separator structures. The spacer material layers are formed as, or are replaced with, electrically conductive layers, which are laterally recessed selective to the insulating layers and the plurality of dielectric separator structures to form a pair of lateral cavities at each level of the electrically conductive layers in each memory opening. After formation of a blocking dielectric layer, a pair of physically disjoined metal-semiconductor alloy portions are formed in each pair of lateral cavities as floating gate electrodes. A tunneling dielectric layer and a semiconductor channel layer is subsequently formed in each memory opening.


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