The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Sep. 14, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventor:

Artur Antonyan, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 13/00 (2006.01); G11C 7/14 (2006.01); G11C 7/06 (2006.01); G11C 7/08 (2006.01); G11C 11/15 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 7/062 (2013.01); G11C 7/067 (2013.01); G11C 7/08 (2013.01); G11C 7/14 (2013.01); G11C 11/15 (2013.01); G11C 11/1673 (2013.01); G11C 13/004 (2013.01); G11C 11/1659 (2013.01); G11C 11/1693 (2013.01); G11C 13/0061 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0054 (2013.01);
Abstract

A resistive memory device according to an example embodiment of the inventive concepts includes: a cell array including a first section and a second section; a first column switch circuit connected to a memory cell and a reference cell of the first section through first bit lines; a second column switch circuit connected to a memory cell and a reference cell of the second section through second bit lines; and a column decoder configured to control the first and second column switch circuits such that one of the first bit lines connected to the memory cell and one of the second bit lines connected to the reference cell are selected according to a first column address, and one of the first bit lines connected to the reference cell and one of the second bit lines connected to the memory cell are selected according to a second column address.


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