The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Sep. 04, 2018
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Joris Lacord, Saint Blaise du Buis, FR;

François Tcheme Wakam, Sain-Martin-d'Hères, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4096 (2006.01); H01L 27/108 (2006.01); H01L 29/10 (2006.01); G11C 11/404 (2006.01); G11C 11/409 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 11/404 (2013.01); G11C 11/409 (2013.01); H01L 27/10802 (2013.01); H01L 29/1079 (2013.01); H01L 29/1095 (2013.01); G11C 2211/4016 (2013.01);
Abstract

A method for programming a one-transistor dynamic memory cell of A2RAM type. The A2RAM memory cell includes a source and a drain doped of a first conductivity type, a body region arranged between the source and the drain, and an insulated gate arranged facing the body region. The body region includes first and second portions extending parallel to the insulated gate, the first portion being doped of a second conductivity type opposite to the first conductivity type and arranged between the insulated gate and the second portion, doped of the first conductivity type. The programming method includes biasing the transistor in an off state by electrical potentials applied to the drain and the gate. The drain potential and the gate potential are chosen in such a way as to create charge carriers by impact ionisation in the second portion.


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