The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Mar. 30, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Rathinakumar Appuswamy, San Jose, CA (US);

John V. Arthur, Mountain View, CA (US);

Andrew S. Cassidy, San Jose, CA (US);

Pallab Datta, San Jose, CA (US);

Steven K. Esser, San Jose, CA (US);

Myron D. Flickner, San Jose, CA (US);

Jennifer Klamo, San Jose, CA (US);

Dharmendra S. Modha, San Jose, CA (US);

Hartmut Penner, San Jose, CA (US);

Jun Sawada, Austin, TX (US);

Brian Taba, Cupertino, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2006.01); G06F 17/16 (2006.01); G06F 7/53 (2006.01); G06F 7/505 (2006.01); G06F 5/01 (2006.01); H03M 7/30 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 5/01 (2013.01); G06F 7/505 (2013.01); G06F 7/53 (2013.01); G06F 17/16 (2013.01); H03M 7/30 (2013.01);
Abstract

Massively parallel neural inference computing elements are provided. A plurality of multipliers is arranged in a plurality of equal-sized groups. Each of the plurality of multipliers is adapted to, in parallel, apply a weight to an input activation to generate an output. A plurality of adders is operatively coupled to one of the groups of multipliers. Each of the plurality of adders is adapted to, in parallel, add the outputs of the multipliers within its associated group to generate a partial sum. A plurality of function blocks is operatively coupled to one of the plurality of adders. Each of the plurality of function blocks is adapted to, in parallel, apply a function to the partial sum of its associated adder to generate an output value.


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