The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2020

Filed:

Sep. 26, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bin Xing, Hillsboro, OR (US);

Krystof C. Zmudzinski, Forest Grove, OR (US);

Wei Wu, Portland, OR (US);

Shih-Lien L. Lu, Portland, OR (US);

Carlos V. Rozas, Portland, OR (US);

Francis X. McKeen, Portland, OR (US);

Siddhartha Chhabra, Hillsboro, OR (US);

Mark W. Shanahan, Raleigh, NC (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 21/53 (2013.01);
U.S. Cl.
CPC ...
G06F 21/53 (2013.01); G06F 2221/033 (2013.01);
Abstract

Technologies for software attack detection include a computing device with a processor and a memory external to the processor. The processor originates a memory transaction with an associated secure enclave status bit that indicates whether the memory transaction originated in a secure execution mode, such as from a secure enclave. The processor computes an error-correcting code (ECC) based as a function of memory transaction data and the secure enclave status bit, and performs the memory transaction based on the ECC and the memory transaction data using the memory of the computing device. The processor may store the ECC and the memory transaction data to memory. The processor may load a stored ECC and data from the memory and compare the computed ECC to the stored ECC to detect memory transactions with an invalid secure enclave status bit. Other embodiments are described and claimed.


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