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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10615257 B1

PDFFull Text
Date of Patent:
Apr. 07, 2020

Filed:

Sep. 07, 2018

Patterning method for nanosheet transistors

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Injo Ok, Loudonville, NY (US);

Balasubramanian Pranatharthiharan, Watervliet, NY (US);

Wei Wang, Yorktown Heights, NY (US);

Kevin W. Brew, Albany, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Vazken Alexanian

Ryan, Mason & Lewis, LLP

Primary Examiner:

Victoria K Hall

Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 21/3213 (2006.01); H01L 21/3105 (2006.01); H01L 29/66 (2006.01); H01L 21/033 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/02 (2006.01); H01L 29/49 (2006.01); H01L 21/285 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0673 (2013.01); H01L 21/0337 (2013.01); H01L 21/31051 (2013.01); H01L 21/31058 (2013.01); H01L 21/32136 (2013.01); H01L 21/32139 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 21/02164 (2013.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/28568 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01);
Abstract

A semiconductor device includes a first type nanosheet device having a first plurality of nanosheet portions alternately stacked with a first plurality of work function metal layers on a substrate, and a second type nanosheet device having a second plurality of nanosheet portions alternately stacked with a second plurality of work function metal layers on the substrate. The second type nanosheet device is spaced apart from the first type nanosheet device. The semiconductor device also includes a dielectric layer disposed in the space between the first and second type nanosheet devices. The first and second plurality of work function metal layers are directly disposed on the dielectric layer, and bottom surfaces of the directly disposed first and second plurality of work function metal layers are co-planar with each other.

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