The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Jan. 15, 2019
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Heng Cao, Shanghai, CN;

Sheng Fen Chiu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2409 (2013.01); G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); H01L 27/2463 (2013.01); H01L 45/06 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/141 (2013.01); H01L 45/144 (2013.01); H01L 45/145 (2013.01); H01L 45/146 (2013.01); G11C 2013/005 (2013.01); G11C 2013/009 (2013.01); G11C 2213/32 (2013.01); G11C 2213/52 (2013.01); G11C 2213/72 (2013.01); G11C 2213/74 (2013.01);
Abstract

A memory cell includes a bit line and a reset line sharing a same line, a word line, a first diode including a first N-well region in a substrate, and a first P-type doped region adjacent to the first N-well region that is coupled to a set line, a second diode spaced apart from the first diode and including a second N-well region in the substrate, a first N-type doped region and a second P-type doped region spaced apart from each other and adjacent to the second N-well region, the second P-type doped region coupled to the bit line and the reset line, a bottom electrode coupled to the first P-type doped region and the first N-type doped region, a top electrode coupled to the word line, and a data storage material layer disposed between the bottom electrode and the top electrode.


Find Patent Forward Citations

Cao, Heng. (2020). Memory cell, memory cell array and operating method thereof (U.S. Patent No. 10615224). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10615224

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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