The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2020
Filed:
Dec. 15, 2017
Applicant:
Atomera Incorporated, Los Gatos, CA (US);
Inventors:
Assignee:
ATOMERA INCORPORATED, Los Gatos, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/00 (2006.01); H01L 27/146 (2006.01); H01L 29/15 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14634 (2013.01); H01L 27/1469 (2013.01); H01L 27/14616 (2013.01); H01L 27/14621 (2013.01); H01L 27/14627 (2013.01); H01L 27/14636 (2013.01); H01L 27/14645 (2013.01); H01L 27/14685 (2013.01); H01L 27/14689 (2013.01); H01L 29/1033 (2013.01); H01L 29/152 (2013.01); H01L 29/16 (2013.01); H01L 27/1464 (2013.01);
Abstract
A CMOS image sensor may include a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, and a second semiconductor chip coupled to the first semiconductor chip in a stack and including image processing circuitry electrically connected to the readout circuitry. The readout circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.