The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2020
Filed:
Aug. 10, 2017
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Kangguo Cheng, Schenectady, NY (US);
Juntao Li, Cohoes, NY (US);
Geng Wang, Stormville, NY (US);
Qintao Zhang, Mt. Kisco, NY (US);
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 21/8234 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/823487 (2013.01); H01L 29/0873 (2013.01); H01L 29/66659 (2013.01); H01L 29/66666 (2013.01); H01L 29/66681 (2013.01); H01L 29/7817 (2013.01); H01L 29/7827 (2013.01); H01L 29/7833 (2013.01); H01L 29/7835 (2013.01); H01L 29/78642 (2013.01);
Abstract
Embodiments are directed to devices and methods for integrating laterally diffused metal oxide semiconductor (LDMOS) technology on vertical field effect transistor (VFET) technology, which enables VFET applications to be broadened to include power amplifiers. By providing a combined asymmetric underlapped drain, high current, low subthreshold slope and LDMOS lightly doped drain, high drain resistance and high drain voltage are enabled.