The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

Nov. 29, 2017
Applicant:

Pep Innovation Pte Ltd., Singapore, SG;

Inventor:

Hwee Seng Jimmy Chew, Singapore, SG;

Assignee:

PEP INNOVATION PTE LTD., Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/561 (2013.01); H01L 23/3135 (2013.01); H01L 24/02 (2013.01); H01L 24/18 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 24/82 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 21/568 (2013.01); H01L 23/3121 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/24195 (2013.01); H01L 2224/25171 (2013.01); H01L 2224/821 (2013.01); H01L 2224/92144 (2013.01); H01L 2224/95001 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/3511 (2013.01);
Abstract

The present disclosure discloses a method of packaging a chip and a chip package structure. The method of packaging the chip includes: mounting at least one chip to be packaged on a carrier, a back surface of the chip to be packaged facing upwards and an active surface facing towards the carrier; forming a sealing layer, the sealing layer being at least wrapped around the at least one chip to be packaged; forming a first encapsulation layer, wherein the first encapsulation layer covers the entire carrier for encapsulating the at least one chip to be packaged and the sealing layer; detaching the carrier to expose the active surface of the at least one chip to be packaged; and completing the packaging by a rewiring process on the active surface of the at least one chip to be packaged. The active surface of the chip to be packaged is mounted on the carrier, and the chip to be packaged is fixed on the carrier at a predetermined position by the sealing layer, so that the position of the chip to be packaged in the subsequent process is not easily moved.


Find Patent Forward Citations

Loading…