The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Jan. 05, 2018
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Biman Chattopadhyay, Karnataka, IN;

Ravi Mehta, Karnataka, IN;

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); H03L 7/08 (2006.01); H04L 7/00 (2006.01); H03L 7/091 (2006.01); H04L 7/033 (2006.01); H03L 7/099 (2006.01); H03L 7/087 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0807 (2013.01); H03L 7/087 (2013.01); H03L 7/091 (2013.01); H03L 7/099 (2013.01); H04L 7/0025 (2013.01); H04L 7/033 (2013.01); H03L 2207/06 (2013.01);
Abstract

A clock and data recovery circuit includes a bang-bang phase detector (BBPD), a voltage controlled oscillator (VCO), a frequency control circuit, and an up-down counter. The BBPD generates an early-late signal by determining whether serialized data received by the BBPD is early or late with respect to a VCO clock signal generated by the VCO. A phase of the VCO clock signal is controlled based on the early-late signal. The frequency control circuit compares a frequency of the VCO clock signal and a target frequency and generates an up/down signal. Based on the up/down signal, the up-down counter increments or decrements the frequency of the VCO clock signal to match the target frequency.


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