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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10608092 B1

PDFFull Text
Date of Patent:
Mar. 31, 2020

Filed:

Dec. 16, 2017

Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts

Applicant:

Alpha and Omega Semiconductor Incorporated, Sunnyvale, CA (US);

Inventors:

Hamza Yilmaz, Saratoga, CA (US);

John Chen, Palo Alto, CA (US);

Daniel Ng, Campbell, CA (US);

Wenjun Li, Songjiang Shanghai, CN;

Assignee:

Alpha and Omega Semiconductor Incorporated, Sunnyvale, CA (US);

Attorney:

Bo-In Lin

Primary Examiner:

Savitr Mulpuri

Int. Cl.
CPC ...
H01L 21/306 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/40 (2006.01); H01L 29/49 (2006.01); H01L 29/10 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01); H01L 29/872 (2006.01); H01L 29/861 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4236 (2013.01); H01L 21/3065 (2013.01); H01L 21/823487 (2013.01); H01L 27/0255 (2013.01); H01L 29/0619 (2013.01); H01L 29/1095 (2013.01); H01L 29/407 (2013.01); H01L 29/4975 (2013.01); H01L 29/66136 (2013.01); H01L 29/66143 (2013.01); H01L 29/66666 (2013.01); H01L 29/66674 (2013.01); H01L 29/66734 (2013.01); H01L 29/7806 (2013.01); H01L 29/7827 (2013.01); H01L 29/861 (2013.01); H01L 29/872 (2013.01); H01L 29/8725 (2013.01);
Abstract

This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.

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