The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2020
Filed:
Oct. 01, 2018
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Takayuki Iwaki, Hiroshima, JP;
Akira Kaneko, Hiroshima, JP;
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10855 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01); H01L 27/10882 (2013.01); H01L 21/02271 (2013.01); H01L 21/02326 (2013.01); H01L 21/31111 (2013.01);
Abstract
A method of forming a plurality of conductive vias comprises forming spaced contact openings individually having two opposing sidewalls comprising SiBON, where 'w' is from 0.1 to 0.3, 'x' is from 0.1 to 0.4, “y” is from 0 to 0.2, and “z” is from 0.4 to 0.6. A lining comprising silicon nitride is formed over the two opposing sidewalls in individual of the contact openings. A conductive via is formed in the individual contact openings over the lining. Integrated circuitry is disclosed.