The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

May. 01, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yun Hyeok Im, Hwaseong-si, KR;

Hee Seok Lee, Suwon-si, KR;

Tae Woo Kang, Suwon-si, KR;

Yeong Seok Kim, Seongnam-si, KR;

Kyoung-Min Lee, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 25/10 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 23/3675 (2013.01); H01L 23/3677 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/5385 (2013.01); H01L 23/5389 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

The semiconductor package including a first semiconductor package including a first semiconductor package substrate, and a first semiconductor chip on the first semiconductor package substrate, an interposer disposed on the first semiconductor package is provided. Interposer electrically connects the first semiconductor package with an external semiconductor package, and has first and second sides opposed to each other. The second side is located between the first side and the first semiconductor package substrate, a first recess is formed in the second side of the interposer. The first recess has side walls extended from the second side toward the first side of the interposer and an upper surface connected to the side walls and the upper surface of the first recess faces the first semiconductor chip and a via in the interposer. The via does not transmit an electrical signal between the first semiconductor package and the external semiconductor package.


Find Patent Forward Citations

Loading…