The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Aug. 23, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jae Hyun Lim, Suwon-si, KR;

Han Kim, Suwon-si, KR;

Yoon Seok Seo, Suwon-si, KR;

Sang Jong Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 25/105 (2013.01); H01L 23/49827 (2013.01); H01L 24/48 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/107 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19101 (2013.01);
Abstract

A semiconductor package includes a first semiconductor package including a core member having a through-hole, a first semiconductor chip disposed in the through-hole and having an active surface with a connection pad disposed thereon, a first encapsulant for encapsulating at least a portion of the first semiconductor chip, and a connection member disposed on the active surface of the first semiconductor chip and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, a second semiconductor package disposed on the first semiconductor package and including a wiring substrate electrically connected to the connection member, at least one second semiconductor chip disposed on the wiring substrate, and a second encapsulant for encapsulating at least a portion of the second semiconductor chip, and a heat dissipation member covering a lateral surface of the second semiconductor package and exposing an upper surface of the second encapsulant.


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