The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Sep. 06, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Michael J. Bernhardt, Boise, ID (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 27/11526 (2017.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0007 (2013.01); G11C 13/0021 (2013.01); H01L 27/11526 (2013.01); H01L 27/2481 (2013.01); H01L 45/1253 (2013.01); H01L 45/145 (2013.01); G11C 13/003 (2013.01); G11C 2213/71 (2013.01); G11C 2213/76 (2013.01); G11C 2213/81 (2013.01); H01L 27/224 (2013.01); H01L 27/2409 (2013.01); H01L 2224/16225 (2013.01);
Abstract

Embodiments of the present disclosure are directed towards techniques to provide structural integrity for a memory device comprising a memory array. In one embodiment, the device may comprise a memory array having at least a plurality of wordlines disposed in a memory region of a die, and a first fill layer deposited between adjacent wordlines of the plurality of wordlines in the memory region, to provide structural integrity for the memory array. At least a portion of a periphery region of the die adjacent to the memory region may be substantially filled with a second fill layer that is different than the first fill layer. Other embodiments may be described and/or claimed.


Find Patent Forward Citations

Loading…