The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Apr. 03, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Michael A Kazda, Poughkeepsie, NY (US);

Diwesh Pandey, Bangalore, IN;

Sven Peyer, Tuebingen, DE;

Gustavo E Tellez, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H03K 19/17736 (2020.01); H03K 19/17752 (2020.01); H03K 19/17756 (2020.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01); G06F 17/5045 (2013.01); G06F 17/5072 (2013.01); G06F 17/5081 (2013.01); H03K 19/1774 (2013.01); H03K 19/17752 (2013.01); H03K 19/17756 (2013.01); G06F 2217/84 (2013.01);
Abstract

A router is used to produce a first integrated circuit structure according to an engineering change order. An initial detail routing topology is imported for the first integrated circuit structure. An engineering change order is received instructing the router to change a portion of the initial detail routing topology for the first integrated circuit structure. A global routing operation is performed which routes global wires for the portion of the initial detail routing topology for the first integrated circuit structure. For each global wire which is routed, a specific global wiring track is selected for the global wire within each edge of a set of global tiles in a routing topology for the first integrated circuit.


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