The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Sep. 20, 2013
Applicant:

Cree, Inc., Durham, NC (US);

Inventors:

Edward Robert Van Brunt, Raleigh, NC (US);

Vipindas Pala, Morrisville, NC (US);

Lin Cheng, Chapel Hill, NC (US);

Assignee:

Cree, Inc., Durham, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/47 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7806 (2013.01); H01L 29/66068 (2013.01); H01L 29/66712 (2013.01); H01L 29/0619 (2013.01); H01L 29/0696 (2013.01); H01L 29/0878 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/47 (2013.01);
Abstract

A semiconductor device includes a vertical FET device and a Schottky bypass diode. The vertical FET device includes a gate contact, a source contact, and a drain contact. The gate contact and the source contact are separated from the drain contact by at least a drift layer. The Schottky bypass diode is coupled between the source contact and the drain contact and monolithically integrated adjacent to the vertical FET device such that a voltage placed between the source contact and the drain contact is distributed throughout the drift layer by the Schottky bypass diode in such a way that a voltage across each one of a plurality of P-N junctions formed between the source contact and the drain contact within the vertical FET device is prevented from exceeding a barrier voltage of the respective P-N junction.


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