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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10600802 B1

PDFFull Text
Date of Patent:
Mar. 24, 2020

Filed:

Mar. 07, 2018

Multi-tier memory device with rounded top part of joint structure and methods of making the same

Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Tadashi Nakamura, Yokkaichi, JP;

Kota Funayama, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:

The Marbury Law Group PLLC

Primary Examiner:

Jarrett J Stark

Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 29/788 (2006.01); H01L 29/10 (2006.01); H01L 21/311 (2006.01); H01L 29/66 (2006.01); H01L 21/3105 (2006.01); H01L 21/02 (2006.01); H01L 27/11556 (2017.01); H01L 21/28 (2006.01); H01L 27/11519 (2017.01); H01L 27/11526 (2017.01); H01L 27/11521 (2017.01); H01L 27/11565 (2017.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 29/792 (2006.01); H01L 27/11529 (2017.01); H01L 27/11524 (2017.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0223 (2013.01); H01L 21/02164 (2013.01); H01L 21/02636 (2013.01); H01L 21/31051 (2013.01); H01L 21/31111 (2013.01); H01L 27/11556 (2013.01); H01L 29/1037 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/6653 (2013.01); H01L 29/7883 (2013.01); H01L 21/0217 (2013.01); H01L 21/02211 (2013.01); H01L 21/02271 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11529 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01);
Abstract

A first alternating stack of first insulating layers and first spacer layers, an inter-tier dielectric layer, a sacrificial memory opening fill structure, and a second alternating stack of second insulating layers and second spacer layers are formed over a substrate. The spacer layers are formed as, or are subsequently replaced with, electrically conductive layers. A concave downward-facing surface of the inter-tier dielectric layer is formed on a convex upper surface of the sacrificial memory opening fill structure. An inter-tier memory opening is provided by forming second-tier memory opening and removing the sacrificial memory opening fill structure. A memory stack structure including a memory film is formed in the inter-tier memory opening. The memory film includes a rounded top surface at the joint between tiers to enhance its reliability.

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