The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Sep. 05, 2018
Applicant:

Greenliant Ip, Llc, Santa Clara, CA (US);

Inventor:

Bing Yeh, Los Altos Hills, CA (US);

Assignee:

GREENLIANT IP LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 27/11556 (2017.01); H01L 21/28 (2006.01); G11C 16/26 (2006.01); H01L 29/788 (2006.01); H01L 27/11521 (2017.01); H01L 29/66 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/24 (2006.01); H01L 23/522 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); G11C 16/0416 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H01L 23/5222 (2013.01); H01L 27/11521 (2013.01); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H01L 29/42336 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01); G11C 2216/04 (2013.01);
Abstract

An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, a channel region between the first substrate region and the bottom portion of the trench region, an electrically conductive control gate insulated from and disposed over the first channel portion, an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region, an insulation region disposed over the second channel portion between the control gate and the second floating gate portion, an electrically conductive source line insulated from the floating gate and electrically connected to the trench region of the substrate, and an electrically conductive erase gate insulated from and disposed over a tip of the floating gate.


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