The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Jan. 26, 2018
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Jim Dobbins, Santa Clara, CA (US);

Sheetal Jain, Santa Clara, CA (US);

Don Templeton, Santa Clara, CA (US);

Yaping Zhou, Santa Clara, CA (US);

Wenjun Shi, Santa Clara, CA (US);

Sunil Sudhakaran, Santa Clara, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/66 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5221 (2013.01); H01L 21/76895 (2013.01); H01L 23/66 (2013.01); H01L 2223/6638 (2013.01);
Abstract

In one embodiment, a system comprises: a plurality of aggressor bus lines; and a plurality of differential pair bus lines that are located in relatively parallel close proximity to the plurality of aggressor bus lines, wherein at least two of the plurality of differential pair bus lines change location with respect to each other at a point that has a cancelling affect on cross talk from the plurality of aggressor bus lines, wherein the change includes cross over routing. The plurality of differential pair bus lines can convey differential clock signals. The routing of the plurality of differential pair bus lines is substantially parallel to one another before and after the change.


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