The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2020
Filed:
Apr. 13, 2018
Applicant:
General Electric Company, Schenectady, NY (US);
Inventors:
Alexander Viktorovich Bolotnikov, Niskayuna, NY (US);
Peter Almern Losee, Clifton Park, NY (US);
Reza Ghandi, Niskayuna, NY (US);
David Alan Lilienfeld, Niskayuna, NY (US);
Assignee:
GENERAL ELECTRIC COMPANY, Niskayuna, NY (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/04 (2006.01); H01L 29/36 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/16 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0465 (2013.01); H01L 29/0634 (2013.01); H01L 29/36 (2013.01); H01L 29/66068 (2013.01); H01L 29/7802 (2013.01); H01L 29/7811 (2013.01); H01L 29/0623 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01);
Abstract
A method of manufacturing a semiconductor device including performing a first implantation in a semiconductor layer via ion implantation forming a first implantation region and performing a second implantation in the semiconductor layer via ion implantation forming a second implantation region. The first and second implantation overlap with one another and combine to form a connection region extending into the semiconductor layer by a predefined depth.