Methods for operating ferroelectric memory cells each having multiple capacitors

Abstract

Embodiments of methods for operating ferroelectric memory cells are disclosed. In one example, a method for writing a ferroelectric memory cell is provided. The ferroelectric memory cell includes a transistor and N capacitors. The transistor is electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a respective one of N plate lines in parallel. A plate line signal pulsed between 0 V and Vdd is applied to each of the N plate lines according to a plate line time sequence. A bit line signal pulsed between 0 V and the Vdd is applied to the bit line according to a bit line time sequence to write a valid state of data into the N capacitors. The data consists of N+1 valid states that can be written into the N capacitors. The valid states of the data are determined based on the plate line time sequence. The bit line time sequence is determined based on the valid state of the data written into the N capacitors.