The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Jun. 12, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Erik Hallnor, Beaverton, OR (US);

Matthew Erler, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/0811 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 3/0629 (2013.01); G06F 3/0673 (2013.01); G06F 12/0811 (2013.01); G06F 2212/1008 (2013.01);
Abstract

Embodiment of this disclosure provides a hierarchical structure of ordering points. In some embodiments, the hierarchical structure includes a single primary ordering point (POP) and at least one (or more) auxiliary order point (AOP) of a processing device. In one implementation, the processing device includes one or more cores; and a coherency circuit, operatively coupled to the cores. The processing device is to receive a plurality of memory access requests to be ordered by a first ordering point of the processing device. The processing device determines whether to stop the first ordering point based on a system event. Responsive to determining that the first ordering point is stopped, a second ordering point of the processing device is identified. Thereupon, a memory access request of the plurality of memory access requests is provided to the second ordering point.


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