The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Jun. 30, 2017
Applicant:

Mstar Semiconductor, Inc., Hsinchu Hsien, TW;

Inventors:

Ming-Han Weng, Hsinchu County, TW;

Wei-Yung Wang, Hsinchu County, TW;

Chih-Hung Lin, Hsinchu County, TW;

Jyun Yang Shih, Hsinchu County, TW;

Chun-Chia Chen, Hsinchu County, TW;

Assignee:

MEDIATEK INC., Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 5/135 (2006.01); H03K 5/151 (2006.01); H03L 7/08 (2006.01); H03L 7/091 (2006.01); G01S 13/28 (2006.01); H04N 7/18 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G01S 13/288 (2013.01); H03K 5/135 (2013.01); H03K 5/151 (2013.01); H03L 7/0805 (2013.01); H03L 7/0807 (2013.01); H03L 7/091 (2013.01); H04N 7/188 (2013.01); G11C 7/222 (2013.01);
Abstract

An electronic device includes a clock generating circuit, a receiving circuit and a training circuit. The clock generating circuit generates a sampling clock signal, a phase-early sampling clock signal and a phase-late sampling clock signal. The receiving circuit samples received data according to the sampling clock signal, the phase-early sampling clock signal and the phase-late sampling clock signal to generate a sample result. The training circuit controls the clock generating circuit to generate the sampling clock signal and the corresponding phase-early sampling clock signal and phase-late sampling clock signal that have different phases in a plurality of different time intervals, respectively, to cause the receiving circuit to generate a plurality of sample results. The training circuit further determines a sampling phase of the sampling clock signal according to the sample results.


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