The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2020

Filed:

Nov. 13, 2018
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventors:

Chihtung Chen, San Diego, CA (US);

Yi-Te Yeh, Hsinchu County, TW;

Chia-Hsien Cheng, Hsinchu, TW;

I-Chang Wu, Kaohsiung, TW;

Huai-Yu Yen, Taichung, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G06F 11/26 (2006.01); G06F 17/50 (2006.01); G01R 31/3181 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318547 (2013.01); G01R 31/31813 (2013.01); G06F 11/261 (2013.01); G06F 17/5022 (2013.01);
Abstract

A testing method is performed by at least one processor and includes following operations: converting first data associated with a scan test into a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; performing circuit simulations with the program according to a netlist file indicating the circuitry and testing patterns, in order to rank the testing patterns to generate second data; selecting at least one candidate testing pattern from the testing patterns according to the second data; and performing at least one fault simulation on the circuitry according to the netlist file and the at least one candidate testing pattern, in order to test the circuitry.


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