Digital phase locked loop clock synthesizer with image cancellation

Abstract

A frequency synthesizer includes a hardware digital controlled oscillator (HDCO) running at a first clock rate ffor generating an output clock signal in response to a control input, and a digital phase locked loop (DPLL) responsive to a reference input sampled at a second clock rate f, the first clock rate fbeing N times greater than the second clock rate f, The DPLL includes a loop filter and a software digital controlled oscillator (SDCO). A first, first order linear interpolation anti-imaging filter running at a clock rate higher than said second clock rate fis coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.