The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2020
Filed:
Aug. 30, 2018
Applicant:
Mitsubishi Electric Corporation, Tokyo, JP;
Inventors:
Assignee:
Mitsubishi Electric Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/10 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/36 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7397 (2013.01); H01L 21/26513 (2013.01); H01L 29/0619 (2013.01); H01L 29/0638 (2013.01); H01L 29/1095 (2013.01); H01L 29/36 (2013.01); H01L 29/4238 (2013.01); H01L 29/66333 (2013.01); H01L 29/66348 (2013.01); H01L 29/7395 (2013.01); H01L 29/402 (2013.01);
Abstract
A semiconductor apparatus includes a semiconductor substrate including a semiconductor device. The semiconductor device includes a first n-type buffer layer, a second n-type buffer layer, and a first p-type semiconductor region. A first maximum peak concentration of first n-type carriers contained in the first n-type buffer layer is smaller than a second maximum peak concentration of second n-type carriers contained in the second n-type buffer layer. The first p-type semiconductor region is formed in the first n-type buffer layer. The first p-type semiconductor region has a narrower width than the first n-type buffer layer.