The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Dec. 27, 2016
Applicant:

Infineon Technologies Americas Corp., El Segundo, CA (US);

Inventors:

Hugo Burke, Llantrisant, GB;

Kapil Kelkar, Torrance, CA (US);

Ling Ma, Redondo Beach, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 23/522 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 23/528 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 23/5226 (2013.01); H01L 23/5228 (2013.01); H01L 23/5283 (2013.01); H01L 29/1095 (2013.01); H01L 29/404 (2013.01); H01L 29/407 (2013.01); H01L 29/4236 (2013.01); H01L 29/66348 (2013.01); H01L 29/66734 (2013.01); H01L 29/7803 (2013.01); H01L 29/7813 (2013.01); H01L 29/0692 (2013.01); H01L 29/0696 (2013.01); H01L 29/7397 (2013.01);
Abstract

A semiconductor substrate has a main surface, a rear surface, an active device region, and an inactive region adjacent the active device region. Doped source, body, drift and drain regions, and electrically conductive gate and field electrodes are disposed in the active device region. The gate electrode is configured to control an electrical connection between the source and drain regions. The field electrode is adjacent to the drift region. An intermetal dielectric layer is disposed on the main surface, an electrically conductive source pad is formed in a first metallization layer that is formed on the intermetal dielectric layer. A resistor is connected between the source pad and the field electrode. The resistor includes an electrically conductive resistance section that is disposed in a resistor trench. The resistor trench is formed within the inactive region and is electrically isolated from every active device within the active device region.


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