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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10593600 B1

PDFFull Text
Date of Patent:
Mar. 17, 2020

Filed:

Feb. 24, 2016

Distinct gate stacks for iii-v-based cmos circuits comprising a channel cap

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Takashi Ando, Tuckahoe, NY (US);

Martin M. Frank, Dobbs Ferry, NY (US);

Renee T. Mo, Yorktown Heights, NY (US);

Vijay Narayanan, New York, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Tutunjian & Bitetto, P.C.

Vazken Alexanian

Primary Examiner:

Lex H Malsawma

Assistant Examiner:

Xia L Cross

Int. Cl.
CPC ...
H01L 21/8258 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/8252 (2006.01); H01L 29/267 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8258 (2013.01); H01L 21/8238 (2013.01); H01L 21/8252 (2013.01); H01L 21/823807 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 27/092 (2013.01); H01L 29/1054 (2013.01); H01L 29/267 (2013.01); H01L 29/66568 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01);
Abstract

Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

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