The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Jun. 12, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Larry Seiler, Boylston, MA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 15/04 (2011.01); G06T 11/00 (2006.01);
U.S. Cl.
CPC ...
G06T 15/04 (2013.01); G06T 11/001 (2013.01);
Abstract

A mechanism is described for facilitating increased precision in large mip-mapped stitched textures for graphics computing devices. A method of embodiments, as described herein, includes detecting a stitched texture associated with a first frame of contents associated with an application, and a first region of interest in the stitched texture, where the stitched texture includes a mip-mapped stitched texture associated with multiple mip-levels in a mip-chain. The method may further include defining, at a first mip-level, a tile offset at a position within the first region of interest, where the first mip-level corresponds to the first frame. The method may further include creating or modifying a view of the stitched texture to specify the tile offset, and rendering the stitched texture as a normal texture with a full sub-texel precision.


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