The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10592703 B1

Date of Patent:

Mar. 17, 2020

Filed:

Dec. 01, 2018

Method and system for processing verification tests for testing a design under test

Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventor:

Meir Ovadia, Rosh Ha-Ayin, IL;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:

Pearl Cohen Zedek Latzer Baratz LLP

Primary Examiner:

Phallaka Kik

Int. Cl.

CPC ...

G06F 17/50 (2006.01); G01R 31/28 (2006.01); G06F 30/3323 (2020.01); G06F 30/3312 (2020.01); G06F 119/12 (2020.01);

U.S. Cl.

CPC ...

G06F 30/3323 (2020.01); G06F 30/3312 (2020.01); G01R 31/28 (2013.01); G06F 2119/12 (2020.01);

Abstract

A method for processing verification tests for testing a design under test (DUT), may include receiving from a user a start time message and an end time message for each action of actions in a verification test in a target code form, to be printed into a log file of an execution of the test, so as to list chronologically the start time and end time of each of the actions in the log file. The method may also include executing the verification test to obtain the log file with the start time and end time messages and, using a processor, analyzing the log file to construct a graph representation of the validation test, based on the printed start and end times of the actions of the test.

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