The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Jun. 06, 2017
Applicant:

Crossbar, Inc., Santa Clara, CA (US);

Inventors:

Mehdi Asnaashari, Danville, CA (US);

Robin Sarno, Pleasanton, CA (US);

Ruchirkumar D. Shah, San Jose, CA (US);

Assignee:

CROSSBAR, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/1045 (2016.01); G06F 12/1009 (2016.01); G11C 11/406 (2006.01); G06F 12/02 (2006.01); G06F 12/0802 (2016.01); G06F 12/0815 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1054 (2013.01); G06F 12/0246 (2013.01); G06F 12/0802 (2013.01); G06F 12/0815 (2013.01); G06F 12/1009 (2013.01); G11C 11/40603 (2013.01); H05K 2201/10651 (2013.01);
Abstract

Cache memory for resistive switching memory modules is provided herein. The cache memory can reside on a separate DIMM from the resistive switching memory, in some embodiments, or can share a common DIMM with the resistive switching memory. Cache management protocols are provided to service read and write policies for managing interaction of data between the cache memory and the resistive switching memory. In various embodiments, memory controllers are optimized for physical characteristics of resistive switching memory, and cache management protocols can be implemented to take advantage of these characteristics.


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