The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Feb. 07, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Giri P. Mudusuru, Portland, OR (US);

Rangasai V. Chaganty, Hillsboro, OR (US);

Chasel Chiu, Taipei, TW;

Satya P. Yarlagadda, Bangalore, IN;

Nivedita Aggarwal, Bangaloreii, IN;

Nuo Zhang, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/4401 (2018.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4401 (2013.01); G06F 3/065 (2013.01); G06F 3/0619 (2013.01); G06F 3/0679 (2013.01); G06F 9/4403 (2013.01);
Abstract

Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.


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