The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

May. 13, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Joo-sung Yun, Asan-si, KR;

Soon-il Kwon, Asan-si, KR;

Byeong-min Yu, Asan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); H03K 19/1776 (2020.01); H03K 19/17704 (2020.01);
U.S. Cl.
CPC ...
G01R 31/318519 (2013.01); H03K 19/1776 (2013.01); H03K 19/17704 (2013.01);
Abstract

Provided are a test board and a test system for efficiently testing a semiconductor package, and a manufacturing method for the semiconductor package using the same. A test apparatus includes a field programmable gate array (FPGA) configured to output a first data signal to be transmitted to the semiconductor device and a second data signal to be transmitted to the semiconductor device and a memory configured to store a test result. The FPGA includes a first input/output block configured to output the first data signal, a second input/output block configured to output the second data signal, a serializer/deserializer (SerDes) circuit configured to generate a strobe signal, and a skew calibration input/output block configured to receive the first data signal from the first input/output block, the second data signal from the second input/output block, and the strobe signal from the SerDes circuit.


Find Patent Forward Citations

Loading…