The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Jan. 24, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Harry Barowski, Boeblingen, DE;

Werner Juchmes, Boeblingen, DE;

Michael B. Kugel, Boeblingen, DE;

Wolfgang Penth, Holzgerlingen, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01); G11C 11/413 (2006.01); G01R 31/317 (2006.01); G11C 7/22 (2006.01); G11C 29/50 (2006.01); G11C 29/12 (2006.01); G11C 29/32 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0375 (2013.01); G01R 31/31725 (2013.01); G01R 31/31727 (2013.01); G01R 31/318541 (2013.01); G11C 7/22 (2013.01); G11C 11/413 (2013.01); G11C 29/12015 (2013.01); G11C 29/32 (2013.01); G11C 29/50 (2013.01); G11C 7/222 (2013.01);
Abstract

Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.


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