The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Feb. 27, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventor:

Atsushi Konno, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 27/11565 (2017.01); H01L 27/11573 (2017.01); H01L 27/11575 (2017.01); H01L 27/11519 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes a first electrode layer having a first area, a second area, and a connection area connecting the first area to the second area, and a plurality of semiconductor pillars extending in a first direction through the first electrode layer in the first area and the second area. The plurality of semiconductor pillars are arranged in an array in a second direction and in a third direction intersecting with the second direction, the second direction and the third direction being parallel to the surface of the first electrode layer, and the connection area has no semiconductor pillars disposed therein.


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Konno, Atsushi. (2020). Semiconductor memory device (U.S. Patent No. 10586805). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10586805

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