The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2020
Filed:
Feb. 01, 2018
Applicant:
United Microelectronics Corp., Hsinchu, TW;
Inventors:
Kai-Kuen Chang, Keelung, TW;
Shih-Yin Hsiao, Chiayi County, TW;
Assignee:
United Microelectronics Corp., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823462 (2013.01); H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 27/088 (2013.01); H01L 27/0922 (2013.01); H01L 29/0847 (2013.01); H01L 29/42364 (2013.01); H01L 29/7836 (2013.01);
Abstract
A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.