The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2020
Filed:
Jun. 18, 2018
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventor:
Ming-Yeh Chuang, McKinney, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/761 (2006.01); H01L 29/40 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76202 (2013.01); H01L 21/761 (2013.01); H01L 21/762 (2013.01); H01L 21/76208 (2013.01); H01L 29/0623 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/408 (2013.01); H01L 29/42364 (2013.01); H01L 29/66568 (2013.01); H01L 29/66681 (2013.01); H01L 29/7823 (2013.01); H01L 29/7833 (2013.01); H01L 29/0692 (2013.01);
Abstract
An electronic device includes an isolated region surrounded by an isolation ring over a semiconductor substrate. A well of a first conductivity type is located within the isolated region. A source region and a drain region of a second conductivity type are located over the well. A local-oxidation-of-silicon (LOCOS) layer is located on the well between the source and the drain, between the source and the isolation ring, and between the drain and the isolation ring. A gate electrode located between the source and the drain on said LOCOS layer.